From: Sexton, Rory Date: Tue, 5 Jun 2018 08:26:51 +0000 (+0100) Subject: Extending turbostat plugin to report the following platform metrics: X-Git-Url: https://git.verplant.org/?a=commitdiff_plain;h=3f011bf56fc53e59f685826f8a62e7dd215deee5;p=collectd.git Extending turbostat plugin to report the following platform metrics: - P-states enabled/disabled - Turboboost enabled/disabled - Platform TDP (Thermal Design Point) - Uncore bus ratio --- diff --git a/src/msr-index.h b/src/msr-index.h index 2adca577..d56a3b34 100644 --- a/src/msr-index.h +++ b/src/msr-index.h @@ -33,56 +33,55 @@ /* Intel MSRs. Some also available on other CPUs */ /* C-state Residency Counters */ -#define MSR_PKG_C3_RESIDENCY 0x000003f8 -#define MSR_PKG_C6_RESIDENCY 0x000003f9 -#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa -#define MSR_PKG_C7_RESIDENCY 0x000003fa -#define MSR_CORE_C3_RESIDENCY 0x000003fc -#define MSR_CORE_C6_RESIDENCY 0x000003fd -#define MSR_CORE_C7_RESIDENCY 0x000003fe -#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff -#define MSR_PKG_C2_RESIDENCY 0x0000060d -#define MSR_PKG_C8_RESIDENCY 0x00000630 -#define MSR_PKG_C9_RESIDENCY 0x00000631 -#define MSR_PKG_C10_RESIDENCY 0x00000632 +#define MSR_PKG_C3_RESIDENCY 0x000003f8 +#define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa +#define MSR_PKG_C7_RESIDENCY 0x000003fa +#define MSR_CORE_C3_RESIDENCY 0x000003fc +#define MSR_CORE_C6_RESIDENCY 0x000003fd +#define MSR_CORE_C7_RESIDENCY 0x000003fe +#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff +#define MSR_PKG_C2_RESIDENCY 0x0000060d +#define MSR_PKG_C8_RESIDENCY 0x00000630 +#define MSR_PKG_C9_RESIDENCY 0x00000631 +#define MSR_PKG_C10_RESIDENCY 0x00000632 /* Run Time Average Power Limiting (RAPL) Interface */ -#define MSR_RAPL_POWER_UNIT 0x00000606 +#define MSR_RAPL_POWER_UNIT 0x00000606 -#define MSR_PKG_POWER_LIMIT 0x00000610 -#define MSR_PKG_ENERGY_STATUS 0x00000611 -#define MSR_PKG_PERF_STATUS 0x00000613 -#define MSR_PKG_POWER_INFO 0x00000614 +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 -#define MSR_DRAM_POWER_LIMIT 0x00000618 -#define MSR_DRAM_ENERGY_STATUS 0x00000619 -#define MSR_DRAM_PERF_STATUS 0x0000061b -#define MSR_DRAM_POWER_INFO 0x0000061c - -#define MSR_PP0_POWER_LIMIT 0x00000638 -#define MSR_PP0_ENERGY_STATUS 0x00000639 -#define MSR_PP0_POLICY 0x0000063a -#define MSR_PP0_PERF_STATUS 0x0000063b - -#define MSR_PP1_POWER_LIMIT 0x00000640 -#define MSR_PP1_ENERGY_STATUS 0x00000641 -#define MSR_PP1_POLICY 0x00000642 +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_UNCORE_FREQ_SCALING 0x00000621 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 /* Intel defined MSRs. */ -#define MSR_IA32_TSC 0x00000010 -#define MSR_SMI_COUNT 0x00000034 - -#define MSR_IA32_MPERF 0x000000e7 -#define MSR_IA32_APERF 0x000000e8 +#define MSR_IA32_TSC 0x00000010 +#define MSR_SMI_COUNT 0x00000034 -#define MSR_IA32_THERM_STATUS 0x0000019c +#define MSR_IA32_MPERF 0x000000e7 +#define MSR_IA32_APERF 0x000000e8 -#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_IA32_THERM_STATUS 0x0000019c -#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 #endif /* _ASM_X86_MSR_INDEX_H */ diff --git a/src/turbostat.c b/src/turbostat.c index 68cf4120..ad58097d 100644 --- a/src/turbostat.c +++ b/src/turbostat.c @@ -129,14 +129,21 @@ static bool apply_config_ptm; */ static unsigned int tcc_activation_temp; +static unsigned int do_power_fields; +#define UFS_PLATFORM (1 << 0) +#define TURBO_PLATFORM (1 << 1) +#define PSTATES_PLATFORM (1 << 2) + static unsigned int do_rapl; static unsigned int config_rapl; static bool apply_config_rapl; static double rapl_energy_units; +static double rapl_power_units; #define RAPL_PKG (1 << 0) /* 0x610 MSR_PKG_POWER_LIMIT */ /* 0x611 MSR_PKG_ENERGY_STATUS */ +/* 0x614 MSR_PKG_POWER_INFO */ #define RAPL_DRAM (1 << 1) /* 0x618 MSR_DRAM_POWER_LIMIT */ /* 0x619 MSR_DRAM_ENERGY_STATUS */ @@ -188,6 +195,10 @@ static struct pkg_data { uint32_t energy_dram; /* MSR_DRAM_ENERGY_STATUS */ uint32_t energy_cores; /* MSR_PP0_ENERGY_STATUS */ uint32_t energy_gfx; /* MSR_PP1_ENERGY_STATUS */ + uint32_t tdp; + uint8_t turbo_enabled; + uint8_t pstates_enabled; + uint32_t uncore; unsigned int tcc_activation_temp; unsigned int pkg_temp_c; } * package_delta, *package_even, *package_odd; @@ -395,6 +406,8 @@ get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) { if (do_rapl & RAPL_PKG) { READ_MSR(MSR_PKG_ENERGY_STATUS, &msr); p->energy_pkg = msr & 0xFFFFFFFF; + READ_MSR(MSR_PKG_POWER_INFO, &msr); + p->tdp = msr & 0x7FFF; } if (do_rapl & RAPL_CORES) { READ_MSR(MSR_PP0_ENERGY_STATUS, &msr); @@ -412,6 +425,18 @@ get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) { READ_MSR(MSR_IA32_PACKAGE_THERM_STATUS, &msr); p->pkg_temp_c = p->tcc_activation_temp - ((msr >> 16) & 0x7F); } + if (do_power_fields && TURBO_PLATFORM) { + READ_MSR(MSR_IA32_MISC_ENABLE, &msr); + p->turbo_enabled = !((msr >> 38) & 0x1); + } + if (do_power_fields && PSTATES_PLATFORM) { + READ_MSR(MSR_IA32_MISC_ENABLE, &msr); + p->pstates_enabled = (msr >> 16) & 0x1; + } + if (do_power_fields && UFS_PLATFORM) { + READ_MSR(MSR_UNCORE_FREQ_SCALING, &msr); + p->uncore = msr & 0x1F; + } out: close(msr_fd); @@ -442,6 +467,11 @@ static inline void delta_package(struct pkg_data *delta, delta->energy_cores = new->energy_cores - old->energy_cores; delta->energy_gfx = new->energy_gfx - old->energy_gfx; delta->energy_dram = new->energy_dram - old->energy_dram; + delta->tdp = new->tdp; + delta->turbo_enabled = new->turbo_enabled; + delta->pstates_enabled = new->pstates_enabled; + delta->tcc_activation_temp = new->tcc_activation_temp; + delta->uncore = new->uncore; } /* @@ -627,9 +657,11 @@ static int submit_counters(struct thread_data *t, struct core_data *c, turbostat_submit(name, "percent", "pc10", 100.0 * p->pc10 / t->tsc); if (do_rapl) { - if (do_rapl & RAPL_PKG) + if (do_rapl & RAPL_PKG) { turbostat_submit(name, "power", "pkg", p->energy_pkg * rapl_energy_units / interval_float); + turbostat_submit(name, "tdp", "pkg", p->tdp * rapl_power_units); + } if (do_rapl & RAPL_CORES) turbostat_submit(name, "power", "cores", p->energy_cores * rapl_energy_units / interval_float); @@ -640,6 +672,18 @@ static int submit_counters(struct thread_data *t, struct core_data *c, turbostat_submit(name, "power", "DRAM", p->energy_dram * rapl_energy_units / interval_float); } + + if (do_power_fields && TURBO_PLATFORM) { + turbostat_submit(name, "turbo_enabled", NULL, p->turbo_enabled); + } + if (do_power_fields && PSTATES_PLATFORM) { + turbostat_submit(name, "pstates_enabled", NULL, p->pstates_enabled); + } + if (do_power_fields && UFS_PLATFORM) { + turbostat_submit(name, "uncore_ratio", NULL, p->uncore); + } + turbostat_submit(name, "temperature", "tcc_activation", + p->tcc_activation_temp); done: return 0; } @@ -985,10 +1029,12 @@ static int __attribute__((warn_unused_result)) probe_cpu(void) { case 0x4F: /* BDX */ case 0x56: /* BDX-DE */ do_rapl = RAPL_PKG | RAPL_DRAM; + do_power_fields = TURBO_PLATFORM | UFS_PLATFORM | PSTATES_PLATFORM; break; case 0x2D: /* SNB Xeon */ case 0x3E: /* IVB Xeon */ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_DRAM; + do_power_fields = TURBO_PLATFORM | PSTATES_PLATFORM; break; case 0x37: /* BYT */ case 0x4D: /* AVN */ @@ -1023,6 +1069,7 @@ static int __attribute__((warn_unused_result)) probe_cpu(void) { if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr)) return 0; + rapl_power_units = 1.0 / (1 << (msr & 0xF)); if (model == 0x37) rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; else diff --git a/src/types.db b/src/types.db index 1b1e6f0c..9975d324 100644 --- a/src/types.db +++ b/src/types.db @@ -208,6 +208,7 @@ ps_rss value:GAUGE:0:9223372036854775807 ps_stacksize value:GAUGE:0:9223372036854775807 ps_state value:GAUGE:0:65535 ps_vm value:GAUGE:0:9223372036854775807 +pstates_enabled value:GAUGE:0:1 pubsub value:GAUGE:0:U queue_length value:GAUGE:0:U records value:GAUGE:0:U @@ -237,6 +238,7 @@ spl value:GAUGE:U:U swap value:GAUGE:0:1099511627776 swap_io value:DERIVE:0:U tcp_connections value:GAUGE:0:4294967295 +tdp value:GAUGE:U:U temperature value:GAUGE:U:U threads value:GAUGE:0:U time_dispersion value:GAUGE:-1000000:1000000 @@ -255,7 +257,9 @@ total_sessions value:DERIVE:0:U total_threads value:DERIVE:0:U total_time_in_ms value:DERIVE:0:U total_values value:DERIVE:0:U +turbo_enabled value:GAUGE:0:1 uptime value:GAUGE:0:4294967295 +uncore_ratio value:GAUGE:0:U users value:GAUGE:0:65535 vcl value:GAUGE:0:65535 vcpu value:GAUGE:0:U