2 * collectd - src/intel_pmu.c
4 * Copyright(c) 2017 Intel Corporation. All rights reserved.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Serhiy Pshyk <serhiyx.pshyk@intel.com>
34 #define PMU_PLUGIN "intel_pmu"
36 #define HW_CACHE_READ_ACCESS \
37 (((PERF_COUNT_HW_CACHE_OP_READ) << 8) | \
38 ((PERF_COUNT_HW_CACHE_RESULT_ACCESS) << 16))
40 #define HW_CACHE_WRITE_ACCESS \
41 (((PERF_COUNT_HW_CACHE_OP_WRITE) << 8) | \
42 ((PERF_COUNT_HW_CACHE_RESULT_ACCESS) << 16))
44 #define HW_CACHE_PREFETCH_ACCESS \
45 (((PERF_COUNT_HW_CACHE_OP_PREFETCH) << 8) | \
46 ((PERF_COUNT_HW_CACHE_RESULT_ACCESS) << 16))
48 #define HW_CACHE_READ_MISS \
49 (((PERF_COUNT_HW_CACHE_OP_READ) << 8) | \
50 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))
52 #define HW_CACHE_WRITE_MISS \
53 (((PERF_COUNT_HW_CACHE_OP_WRITE) << 8) | \
54 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))
56 #define HW_CACHE_PREFETCH_MISS \
57 (((PERF_COUNT_HW_CACHE_OP_PREFETCH) << 8) | \
58 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))
64 typedef struct event_info event_info_t;
66 struct intel_pmu_ctx_s {
67 _Bool hw_cache_events;
68 _Bool kernel_pmu_events;
70 char *hw_specific_events;
71 struct eventlist *event_list;
73 typedef struct intel_pmu_ctx_s intel_pmu_ctx_t;
75 event_info_t g_kernel_pmu_events[] = {
76 {.name = "cpu-cycles", .config = PERF_COUNT_HW_CPU_CYCLES},
77 {.name = "instructions", .config = PERF_COUNT_HW_INSTRUCTIONS},
78 {.name = "cache-references", .config = PERF_COUNT_HW_CACHE_REFERENCES},
79 {.name = "cache-misses", .config = PERF_COUNT_HW_CACHE_MISSES},
80 {.name = "branches", .config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS},
81 {.name = "branch-misses", .config = PERF_COUNT_HW_BRANCH_MISSES},
82 {.name = "bus-cycles", .config = PERF_COUNT_HW_BUS_CYCLES},
85 event_info_t g_hw_cache_events[] = {
87 {.name = "L1-dcache-loads",
88 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_READ_ACCESS)},
89 {.name = "L1-dcache-load-misses",
90 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_READ_MISS)},
91 {.name = "L1-dcache-stores",
92 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_WRITE_ACCESS)},
93 {.name = "L1-dcache-store-misses",
94 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_WRITE_MISS)},
95 {.name = "L1-dcache-prefetches",
96 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_PREFETCH_ACCESS)},
97 {.name = "L1-dcache-prefetch-misses",
98 .config = (PERF_COUNT_HW_CACHE_L1D | HW_CACHE_PREFETCH_MISS)},
100 {.name = "L1-icache-loads",
101 .config = (PERF_COUNT_HW_CACHE_L1I | HW_CACHE_READ_ACCESS)},
102 {.name = "L1-icache-load-misses",
103 .config = (PERF_COUNT_HW_CACHE_L1I | HW_CACHE_READ_MISS)},
104 {.name = "L1-icache-prefetches",
105 .config = (PERF_COUNT_HW_CACHE_L1I | HW_CACHE_PREFETCH_ACCESS)},
106 {.name = "L1-icache-prefetch-misses",
107 .config = (PERF_COUNT_HW_CACHE_L1I | HW_CACHE_PREFETCH_MISS)},
109 {.name = "LLC-loads",
110 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_READ_ACCESS)},
111 {.name = "LLC-load-misses",
112 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_READ_MISS)},
113 {.name = "LLC-stores",
114 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_WRITE_ACCESS)},
115 {.name = "LLC-store-misses",
116 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_WRITE_MISS)},
117 {.name = "LLC-prefetches",
118 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_PREFETCH_ACCESS)},
119 {.name = "LLC-prefetch-misses",
120 .config = (PERF_COUNT_HW_CACHE_LL | HW_CACHE_PREFETCH_MISS)},
122 {.name = "dTLB-loads",
123 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_READ_ACCESS)},
124 {.name = "dTLB-load-misses",
125 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_READ_MISS)},
126 {.name = "dTLB-stores",
127 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_WRITE_ACCESS)},
128 {.name = "dTLB-store-misses",
129 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_WRITE_MISS)},
130 {.name = "dTLB-prefetches",
131 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_PREFETCH_ACCESS)},
132 {.name = "dTLB-prefetch-misses",
133 .config = (PERF_COUNT_HW_CACHE_DTLB | HW_CACHE_PREFETCH_MISS)},
135 {.name = "iTLB-loads",
136 .config = (PERF_COUNT_HW_CACHE_ITLB | HW_CACHE_READ_ACCESS)},
137 {.name = "iTLB-load-misses",
138 .config = (PERF_COUNT_HW_CACHE_ITLB | HW_CACHE_READ_MISS)},
140 {.name = "branch-loads",
141 .config = (PERF_COUNT_HW_CACHE_BPU | HW_CACHE_READ_ACCESS)},
142 {.name = "branch-load-misses",
143 .config = (PERF_COUNT_HW_CACHE_BPU | HW_CACHE_READ_MISS)},
146 event_info_t g_sw_events[] = {
147 {.name = "cpu-clock", .config = PERF_COUNT_SW_CPU_CLOCK},
149 {.name = "task-clock", .config = PERF_COUNT_SW_TASK_CLOCK},
151 {.name = "context-switches", .config = PERF_COUNT_SW_CONTEXT_SWITCHES},
153 {.name = "cpu-migrations", .config = PERF_COUNT_SW_CPU_MIGRATIONS},
155 {.name = "page-faults", .config = PERF_COUNT_SW_PAGE_FAULTS},
157 {.name = "minor-faults", .config = PERF_COUNT_SW_PAGE_FAULTS_MIN},
159 {.name = "major-faults", .config = PERF_COUNT_SW_PAGE_FAULTS_MAJ},
161 {.name = "alignment-faults", .config = PERF_COUNT_SW_ALIGNMENT_FAULTS},
163 {.name = "emulation-faults", .config = PERF_COUNT_SW_EMULATION_FAULTS},
166 static intel_pmu_ctx_t g_ctx;
169 static void pmu_dump_events() {
171 DEBUG(PMU_PLUGIN ": Events:");
175 for (e = g_ctx.event_list->eventlist; e; e = e->next) {
176 DEBUG(PMU_PLUGIN ": event : %s", e->event);
177 DEBUG(PMU_PLUGIN ": group_lead: %d", e->group_leader);
178 DEBUG(PMU_PLUGIN ": end_group : %d", e->end_group);
179 DEBUG(PMU_PLUGIN ": type : 0x%X", e->attr.type);
180 DEBUG(PMU_PLUGIN ": config : 0x%X", (int)e->attr.config);
181 DEBUG(PMU_PLUGIN ": size : %d", e->attr.size);
187 static void pmu_dump_config(void) {
189 DEBUG(PMU_PLUGIN ": Config:");
190 DEBUG(PMU_PLUGIN ": hw_cache_events : %d", g_ctx.hw_cache_events);
191 DEBUG(PMU_PLUGIN ": kernel_pmu_events : %d", g_ctx.kernel_pmu_events);
192 DEBUG(PMU_PLUGIN ": sw_events : %d", g_ctx.sw_events);
193 DEBUG(PMU_PLUGIN ": hw_specific_events: %s", g_ctx.hw_specific_events);
198 #endif /* COLLECT_DEBUG */
200 static int pmu_config(oconfig_item_t *ci) {
203 DEBUG(PMU_PLUGIN ": %s:%d", __FUNCTION__, __LINE__);
205 for (int i = 0; i < ci->children_num; i++) {
206 oconfig_item_t *child = ci->children + i;
208 if (strcasecmp("HWCacheEvents", child->key) == 0) {
209 ret = cf_util_get_boolean(child, &g_ctx.hw_cache_events);
210 } else if (strcasecmp("KernelPMUEvents", child->key) == 0) {
211 ret = cf_util_get_boolean(child, &g_ctx.kernel_pmu_events);
212 } else if (strcasecmp("HWSpecificEvents", child->key) == 0) {
213 ret = cf_util_get_string(child, &g_ctx.hw_specific_events);
214 } else if (strcasecmp("SWEvents", child->key) == 0) {
215 ret = cf_util_get_boolean(child, &g_ctx.sw_events);
217 ERROR(PMU_PLUGIN ": Unknown configuration parameter \"%s\".", child->key);
222 DEBUG(PMU_PLUGIN ": %s:%d ret=%d", __FUNCTION__, __LINE__, ret);
234 static void pmu_submit_counter(int cpu, char *event, counter_t value) {
235 value_list_t vl = VALUE_LIST_INIT;
237 vl.values = &(value_t){.counter = value};
240 sstrncpy(vl.plugin, PMU_PLUGIN, sizeof(vl.plugin));
242 snprintf(vl.plugin_instance, sizeof(vl.plugin_instance), "all");
244 snprintf(vl.plugin_instance, sizeof(vl.plugin_instance), "%d", cpu);
246 sstrncpy(vl.type, "counter", sizeof(vl.type));
247 sstrncpy(vl.type_instance, event, sizeof(vl.type_instance));
249 plugin_dispatch_values(&vl);
252 static int pmu_dispatch_data(void) {
256 for (e = g_ctx.event_list->eventlist; e; e = e->next) {
257 uint64_t all_value = 0;
258 int event_enabled = 0;
259 for (int i = 0; i < g_ctx.event_list->num_cpus; i++) {
261 if (e->efd[i].fd < 0)
266 uint64_t value = event_scaled_value(e, i);
269 /* dispatch per CPU value */
270 pmu_submit_counter(i, e->event, value);
273 if (event_enabled > 0) {
274 DEBUG(PMU_PLUGIN ": %-20s %'10lu", e->event, all_value);
275 /* dispatch all CPU value */
276 pmu_submit_counter(-1, e->event, all_value);
283 static int pmu_read(__attribute__((unused)) user_data_t *ud) {
286 DEBUG(PMU_PLUGIN ": %s:%d", __FUNCTION__, __LINE__);
288 ret = read_all_events(g_ctx.event_list);
290 DEBUG(PMU_PLUGIN ": Failed to read values of all events.");
294 ret = pmu_dispatch_data();
296 DEBUG(PMU_PLUGIN ": Failed to dispatch event values.");
303 static int pmu_add_events(struct eventlist *el, uint32_t type,
304 event_info_t *events, int count) {
306 for (int i = 0; i < count; i++) {
308 calloc(sizeof(struct event) + sizeof(struct efd) * el->num_cpus, 1);
310 ERROR(PMU_PLUGIN ": Failed to allocate event structure");
315 e->attr.config = events[i].config;
316 e->attr.size = PERF_ATTR_SIZE_VER0;
317 e->group_leader = false;
318 e->end_group = false;
322 if (el->eventlist_last)
323 el->eventlist_last->next = e;
324 el->eventlist_last = e;
325 e->event = strdup(events[i].name);
331 static int pmu_parse_events(struct eventlist *el, char *events) {
334 events = strdup(events);
338 for (s = strtok_r(events, ",", &tmp); s; s = strtok_r(NULL, ",", &tmp)) {
339 bool group_leader = false, end_group = false;
345 } else if (len = strlen(s), len > 0 && s[len - 1] == '}') {
351 calloc(sizeof(struct event) + sizeof(struct efd) * el->num_cpus, 1);
357 if (resolve_event(s, &e->attr) == 0) {
358 e->group_leader = group_leader;
359 e->end_group = end_group;
363 if (el->eventlist_last)
364 el->eventlist_last->next = e;
365 el->eventlist_last = e;
366 e->event = strdup(s);
368 DEBUG(PMU_PLUGIN ": Cannot resolve %s", s);
378 static void pmu_free_events(struct eventlist *el) {
383 struct event *e = el->eventlist;
386 struct event *next = e->next;
391 el->eventlist = NULL;
394 static int pmu_setup_events(struct eventlist *el, bool measure_all,
396 struct event *e, *leader = NULL;
399 for (e = el->eventlist; e; e = e->next) {
401 for (int i = 0; i < el->num_cpus; i++) {
402 if (setup_event(e, i, leader, measure_all, measure_pid) < 0) {
403 WARNING(PMU_PLUGIN ": perf event '%s' is not available (cpu=%d).",
406 /* success if at least one event was set */
420 static int pmu_init(void) {
423 DEBUG(PMU_PLUGIN ": %s:%d", __FUNCTION__, __LINE__);
425 g_ctx.event_list = alloc_eventlist();
426 if (g_ctx.event_list == NULL) {
427 ERROR(PMU_PLUGIN ": Failed to allocate event list.");
431 if (g_ctx.hw_cache_events) {
433 pmu_add_events(g_ctx.event_list, PERF_TYPE_HW_CACHE, g_hw_cache_events,
434 STATIC_ARRAY_SIZE(g_hw_cache_events));
436 ERROR(PMU_PLUGIN ": Failed to add hw cache events.");
441 if (g_ctx.kernel_pmu_events) {
442 ret = pmu_add_events(g_ctx.event_list, PERF_TYPE_HARDWARE,
444 STATIC_ARRAY_SIZE(g_kernel_pmu_events));
446 ERROR(PMU_PLUGIN ": Failed to parse kernel PMU events.");
451 /* parse events names if config option is present and is not empty */
452 if (g_ctx.hw_specific_events && (strlen(g_ctx.hw_specific_events) != 0)) {
453 ret = pmu_parse_events(g_ctx.event_list, g_ctx.hw_specific_events);
455 ERROR(PMU_PLUGIN ": Failed to parse hw specific events.");
460 if (g_ctx.sw_events) {
461 ret = pmu_add_events(g_ctx.event_list, PERF_TYPE_SOFTWARE, g_sw_events,
462 STATIC_ARRAY_SIZE(g_sw_events));
464 ERROR(PMU_PLUGIN ": Failed to add software events.");
473 if (g_ctx.event_list->eventlist != NULL) {
474 /* measure all processes */
475 ret = pmu_setup_events(g_ctx.event_list, true, -1);
477 ERROR(PMU_PLUGIN ": Failed to setup perf events for the event list.");
482 ": Events list is empty. No events were setup for monitoring.");
489 pmu_free_events(g_ctx.event_list);
490 sfree(g_ctx.event_list);
491 sfree(g_ctx.hw_specific_events);
496 static int pmu_shutdown(void) {
498 DEBUG(PMU_PLUGIN ": %s:%d", __FUNCTION__, __LINE__);
500 pmu_free_events(g_ctx.event_list);
501 sfree(g_ctx.event_list);
502 sfree(g_ctx.hw_specific_events);
507 void module_register(void) {
508 plugin_register_init(PMU_PLUGIN, pmu_init);
509 plugin_register_complex_config(PMU_PLUGIN, pmu_config);
510 plugin_register_complex_read(NULL, PMU_PLUGIN, pmu_read, 0, NULL);
511 plugin_register_shutdown(PMU_PLUGIN, pmu_shutdown);